Silicon on insulator junctionless field effect transistor (SOI-JLFET) includes a single type doping at the same level in the source, channel, and drain regions. Therefore, its fabrication process is easier than inversion mode SOI-FET. However, SOI-JLFET suffers from high subthreshold slope (SS) as well as high leakage current. As a result, the SOI-JLFET device has limitation for high speed and low power applications. For the first time in this study, use of the auxiliary gate in the drain region of the SOI-JLFET has been proposed to improve the both SS and leakage current parameters. The proposed structure is called "SOI-JLFET Aug". The optimal selection for the auxiliary gate work function and its length, has improved the both SS and ION/IOFF ratio parameters, as compared to Regular SOI-JLFET. Simulation results show that, SOI-JLFET Aug with 20nm channel length exhibits the SS~71mV/dec and ION/IOFF~1013. SS and ON-state to OFF-state current (ION/IOFF) ratio of SOI-JLFET Aug are improved by 14% and three orders of magnitudes, respectively, as compared to the Regular SOI-JLFET. The SOI-JLEFT Aug could be good candidate for digital applications.

Abstract: A detailed study of a novel configuration for junctionless tunneling FET (J-TFET) with extremely low off- (Ioff) and ambipolar current (Iamb) is reported in this paper. In order to achieve desirable on/off current ratio (Ion/Ioff), we have employed voltage difference technique on the gate electrode based on the potential distribution benefits. Main and side gates with an optimum voltage difference creates a stepped potential profile along the channel. This raises the drain side’s bands, reduces the electric field, puts restriction on the flow of charge carriers, and finally remarkable reduction of Iamb from 6.52×10-10 A/µm to 1.14×10-17 A/µm. Also an extremely low subthreshold swing (SS) (22 mV/dec) is achieved thanks to the sharp transition from off- to the on-state. Finally we have investigated the electrical performance of the proposed device for sub-30 nm channel length to examine its immunity against short channel effects. Therefore, our approach renders the novel structure more desirable for the future low power applications.

Abstract:For the first time, in this research, we introduce ajunctionless tunneling FET (J-TFET) on a uniform p+starting junctionless FET to realize appreciable immunityagainst inherent high ambipolar current (Iamb). So, weutilize two isolated gates with appropriate workfunctionsover the channel and drain regions to create P+IP+N+charge distribution. This structure utilizes a spacebetween the gate-drain electrodes (SGD), to provide aP+IP+N+ structure thanks to the effective electronsdepletion on the drain side. Increasing the SGD, furthereffectively pulls up the bands near the interface betweenthe channel-drain regions, widens the tunneling width fortunneling to occur, and thus in turn reduces the Iamb from5.37×10-7 A/µm to 1.14×10-14 A/µm. Thus, we point outthat the proposed J-TFET can obtain on-current thatsatisfies the expectation of logic applications with highperformance and Ioff that meets the specifications of lowpower characteristics, a phenomenon that is rarelyaccessible with conventional TFETs.

This paper proposes a new ultra-compact strip metal-insulator-metal (MIM) plasmonic waveguide on a Silicon-on-insulator (SOI) platform. The waveguide structure can efficiently propagate surface plasmon polaritons (SPPs) within a thin low-index SiO2 layer at an optical wavelength window of 1550 nm. The main parameters of effective refractive index, propagation length, confinement factor, and effective mode area were determined for the proposed waveguide with different waveguide widths. The simulation results were comparable with the in-plane MIM plasmonic waveguide. The proposed layer stack could be monolithically integrated with conventional and hybrid plasmonic SOI-based devices and has the potential of focusing light to nanoscale dimensions.

In this paper in order to improve the electrical performance of nanoscale SOI-junctionless, a targeted modification has been performed. The proposed structure has been aimed to reduce the OFF current and self-heating effect. To reduce the self-heating effect, the buried oxide thickness has been reduced into the half and a part of it has been replaced by a buffer layer. Increase in the thermal conduction and making an extra depletion layer in the buffer layer/channel region interface are led to improvement of the electrical performance in the terms of DC and AC. In the proposed method, which is based on the energy band modification, the parameters such as IOFF, ION/IOFF, subthreshold swing, lattice temperature, voltage gain, transconductance, parasitic capacitances, power gains, cut-off frequency, maximum oscillation frequency and minimum noise figure have been improved. Also, a designing consideration for the role of buffer layer on the proposed device has been performed. Comparing structures under the study simulated by the SILVACO showed the electrical performance superiority for the proposed device.

Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current in DGJL-FET, which is called modified DGJL-FET. In this structure, the channel doping under the gate is the same as the drain and source doping but higher than the mid-channel doping. The simulation results indicated that reducing the thickness of the doped layer under the gate, D, resulted in the reduced OFF-state current. For the proposed device with 10 nm channel length, the OFF-state current is less than that in the regular DGJL-FET by two orders of magnitude. Performance of the regular DGJL-FET and modified DGL-FET for different channel lengths is compared based on the IOFF/ION ratio, sub-threshold slope (SS), and intrinsic gate delay. For modified DGJL-FET, the mid-channel doping and Dare considered as additional parameters for improving the device’s performance in nanometer regime. The simulation results indicated that in the proposed device with channel length of 15 nm, values of SS and IOFF/ION ratio are improved compared to the regular DGJL-FET by 14% and 106 orders of magnitude, respectively.

A comprehensive performance analysis by quantum analytical modeling of CNT on insulator (COI) and CNT on nothing (CON) FET having channel length 20 nm has been proposed and investigated on the basis of 2D Poisson’s Equation and solution of 1-D Schrodinger’s Equation and validated using ATLAS 2D simulator. As classical approximations fail to describe carrier quantization, charge inversion and potential profile of a device at sub-100 nm regime, here for the first time an analytical model in quantum mechanical aspect for COI/CON devices has been derived. Effects of high-k dielectrics in place of conventional SiO2 over the device characteristics have been thoroughly discussed. Moreover, all noticeable benefits of our device to the so called SOI/SON architecture have also been vividly justified.

In this paper, a novel heterostructure junctionless tunnel field effect transistor with Silicon-on-nothing technology (SON HS-JLTFET) is proposed. The proposed device has two advantages over conventional JLTFET. First, one decade of increment in the ON current is achieved and subthreshold swing is improved by 10%. In this device, InAs is used in the source region of SON HS-JLTFET which has a lower energy band gap than Si to achieve thinner tunneling barrier width. Hence, more electron can tunnel from source to channel. As a result, it provides improvements in drain current and subthreshold swing. The second advantage is that the ambipolar current reduction due to the use of SON technique. In fact, in this technique, air is considered as the gate dielectric which results in decrement in the electric field in the drain/channel junction. This reduced electric field causes increasing the width of the tunneling barrier which results in lower ambipolar current in the drain/channel junction..

IIn this paper, we proposed a short channel Silicon on insulator Metal-oxide Semiconductor-Field-Effect-Transistor (SOI-MOSFET), in which a thin layer of n+-type doping has been expanded from top of its entire source region into the channel and also a proportionally heavily p-type retrograde doping has been implanted in its channel, close to the source region. Due to source doping expansion in the channel, we call this structure as Source Expanded Doping Silicon on insulator (SED-SOI) structure. This expanded n+ doping increases the carrier concentration in the source, which can be injected into the channel. Moreover, it increases the amount of carriers, which can be controlled more effectively by the gate electrode. These two advantages enhance both ON state current and transconductance in the device more than 1.9 mA and 5 mS, respectively. Engineered p-type retrograde doping profile causes impurity scattering and this reduces electron mobility in the depth of the device channel, which in turn OFF current decreases down to 0.2 nA. An immense comparison among our proposed device and a conventional structure (C-SOI) shows that it has better performance in terms of Ion/Ioff ratio (>9.5×105), subthreshold swing (75 mV/dec), leakage current, breakdown voltage, hot carrier injection and DIBL. Our analysis demonstrate that SED-SOI transistor can be an excellent candidate for both low power and high performance applications.

In this work, a novel Silicon on insulator (SOI) MOSFET is proposed and investigated. The drain and source electrode structures are optimized to enhance ON-current while global device temperature and hot carrier injection are decreased. In addition, to create an effective heat passage from channel to outside of the device, a Silicon region has embedded in the buried oxide. In order to reduce the device leakage current and controlling the threshold voltage, a p-type retrograde doping is introduced into channel region. Since the air has the least permittivity among materials, it can be utilized to decrease the device parasitic capacitances. Based on this, an air gap is embedded in the buried oxide near the Silicon to improve RF performance of the device. Because the source and drain electrodes are embedded in and over the Silicon film in the source and drain regions, we called this structure EEIOS-SOI MOSFET. “ EEIOS” stands for “ Embedded Electrodes In and Over the Silicon film” . During this work, EEIOS-SOI MOSFET is compared with a conventional SOI MOSFET and another SOI MOSFET with just Embedded Electrodes In the Silicon Film (EEISSOI). EEIS-SOI presents better electrical figure of merits including lower subthreshold slope and lower leakage current in simulations. An immense investigation among these devices shows that EEIOS-SOI MOSFET has better transconductance, lower gate injection leakage current and lower temperature related to DC parameters and higher cut off frequency, gain bandwidth product and unilateral power gain related to AC figures of merits compared to its counterparts.